The present invention relates to a semiconductor memory device and an art which is particularly effective for application, for example, into a large capacity dynamic RAM (Random Access Memory) having a multibit test function.
Some kinds of dynamic RAM have a comparatively large capacity and the so-called multibit test system has been proposed as a method for effectively testing the functions of such dynamic RAM in view of realizing low cost function test.
The multibit test method, for example, has been described in the specification of U.S. Ser. No. 156,897 filed on Feb. 17, 1988.
Investigations by the inventors of the present invention have proved that with improvement in capacity of dynamic RAM, following problem occurs in the multibit test method of the prior art described above. Namely, the dynamic RAM employing such multibit test method is provided with a plurality of memory arrays including a plurality of complementary common data lines and main amplifiers provided corresponding to such memory arrays. When the dynamic RAM is set to the multibit test mode, the one memory cell is respectively set to the selected condition for each complementary data line and the same data is written or read for these memory cells. As a result, when all read data match, the dynamic RAM is judged normal and a high level or low level output signal corresponding to such read data is output. In this case, if the data including difference of even one bit is read out, the dynamic RAM is judged defective, providing a high impedance output.
Namely, in the multibit test method of the prior art described above, it is essential to provide the dynamic RAM with a plurality of complementary common data lines and main amplifiers corresponding to the number of memory cells which are set simultaneously in the selected conditions, namely the number of bits of data simultaneously read or written. It becomes a large factor to interfere high density integration of dynamic RAM and prevent from decrease manufacturing cost when the dynamic RAM has come to have a large capacity such as, for example, 16 Mbits or 64 Mbits. Moreover, when the number of bits to be tested simultaneously in the multibit test mode is reduced in order to avoid such factor, the test cost of dynamic RAM increases on the contrary.